1. Field of the Invention
The present invention relates to a vertical-structured field effect transistor made of GaN-type semiconductors. In particular, the invention relates to a vertical-structured field effect transistor including a source electrode arranged on the top of a GaN-type semiconductor multilayer film and a drain electrode arranged on the bottom of the semiconductor multilayer film, the field effect transistor having a high withstand voltage and being capable of high current operation.
2. Description of the Prior Art
Recently, field effect transistors having a compound semiconductor MES (metal-semiconductor) structure, or MES-FETs, have been developed actively. An MES-FET having a GaN-type compound semiconductor of this kind is typically formed on a semi-insulating sapphire substrate by MOCVD (Metal Organic Chemical Vapor Deposition). Specifically, the MES-FET has a device structure in which an undoped GaN buffer layer is formed on the sapphire substrate, an undoped GaN layer is formed on this GaN buffer layer, and an Si-doped GaN layer is grown as an active layer upon this GaN layer. Then, an SiO2 film is deposited on the surface of the GaN layer (active layer) by plasma CVD or other methods before the SiO2 film is patterned with a photo resist by chemical etching or other methods so that electrode portions are exposed. Subsequently, such metal as Al/Ti/Au is evaporated on the exposed portions to form a source electrode and a drain electrode, respectively. Moreover, Pt/Au is evaporated on as a gate electrode to realize the MES-FET.
Nevertheless, when GaN-type compound semiconductors are used to materialize, for example, an MES-FET that has a high withstand voltage of 500 V or more and is capable of operation under high currents of 10 A or more, there would occur several problems. Specifically, a device structure of planar type in which the source, drain, and gate electrodes are formed on the top surface of the semiconductor device requires an epitaxial wafer of greater area, which means a limit in device size. Besides, thickening a channel to lower the resistance of the channel necessitates increasing the carrier concentration of the channel by using such techniques as double diffusion which is employed in the process of fabricating large scale integrated circuits. This causes troubles including much greater fabrication difficulties. In other words, there remain various kinds of problems in fabricating an MES-FET capable of high current operation from wide-gap compound semiconductors such as GaN and AlGaN.
An object of the present invention is to make effective use of wide-gap, GaN-type compound semiconductors which theoretically have smaller ON-state resistances under operation, thereby realizing a vertical field effect transistor with an MES type structure having a higher withstand voltage and being capable of high current operation.
To achieve the foregoing object, the present invention provides a field effect transistor having a vertical structure including a source electrode formed on the top of a semiconductor multilayer film of GaN type and a drain electrode formed on the bottom of the semiconductor multilayer film, comprising the following first through fifth semiconductor layers.
The first semiconductor layer is composed of a GaN-type semiconductor having a low impurity concentration, and constitutes a current path between the source electrode and drain electrode. This first semiconductor layer is also provided with a groove portion.
The second semiconductor layer is a high-resistance semiconductor layer composed of an undoped GaN-type semiconductor, and is arranged in the groove portion.
The third semiconductor layer is composed of a GaN-type semiconductor having conductivity reverse to that of the first semiconductor layer, and is arranged in the groove portion via the second semiconductor layer.
The fourth semiconductor layer is composed of a GaN-type semiconductor having conductivity identical to that of the first semiconductor layer, and is buried in the third semiconductor layer to constitute a source region.
A source electrode is arranged on the top surface of the source region in the fourth semiconductor layer. A gate electrode is arranged so as to be insulated from the source electrode.
Then, the fifth semiconductor layer is composed of a GaN-type semiconductor having conductivity identical to that of the first semiconductor layer, and is formed to extend from the top of the first semiconductor layer beneath the gate electrode to the fourth semiconductor layer to constitute a channel layer.
That is, the vertical field effect transistor according to the present invention is realized as a vertical-structured MES-FET so that an electric current is passed from the source region (fourth semiconductor layer) through the thin channel layer (fifth semiconductor layer) beneath the gate electrode to flow through the current-path-constituting semiconductor layer of low impurity concentration (first semiconductor layer) to the drain electrode on the backside. In particular, the current-path-constituting first semiconductor layer of low impurity concentration is formed with a greater thickness to increase the source-to-drain distance. In addition, the fifth semiconductor layer which constitutes the channel layer is thinned to reduce the pinch-off voltage. Another feature lies in that the second semiconductor layer of high resistance, made of the undoped GaN-type semiconductor suppresses current leaks through the first and fifth semiconductor layers, thereby enhancing the withstand voltage.
The drain electrode is preferably formed either on the backside of a conductive substrate on which the first semiconductor layer is formed or on the backside of the first semiconductor being rid of the conductive substrate, depending on the thermal conductivity of the conductive substrate. Specifically, when the conductive substrate is made of SiC which has thermal conductivity better than that of GaN, the drain electrode is formed on the backside of the conductive substrate. On the contrary, if sapphire or other material with poor thermal conductivity is used for the conductive substrate, the conductive substrate is eliminated and the drain electrode is formed on the backside of the first semiconductor layer.
The first to fifth semiconductor layers constituting the vertical field effect transistor according to the present invention are preferably formed by gas source MBE (Molecular Beam Epitaxy) or MOCVD (Metal Organic Chemical Vapor Deposition).
More specifically, the vertical field effect transistor according to the present invention is materialized, for example, by making the first semiconductor layer in the form of a lightly-Si-doped nxe2x88x92-GaN layer, the second semiconductor layer an undoped i-GaN layer, the third semiconductor layer a p+-GaN layer, the fourth semiconductor layer an n+-GaN layer, and the fifth semiconductor layer an n+-GaN layer in succession.
According to the present invention, it is possible to provide a vertical field effect transistor that has a device structure in which the semiconductor layer constituting the source region is surrounded by the reverse-conductive semiconductor layer as well as the undoped high-resistance semiconductor layer, and the thin channel layer is formed in the top of a semiconductor layer of low carrier concentration which constitutes the current path.
In addition, according to the present invention, GaN-type semiconductors can be used to provide a field effect transistor having a vertical MES structure, with suppressed leakage currents and the capability of high current operation. Besides, the properties of the GaN-type semiconductors can be fully used to provide a vertical-structured field effect transistor which has a lower ON-state resistance under operation, a high withstand voltage, and excellent temperature characteristics.
Moreover, when the first semiconductor layer has favorable crystallinity, the vertical field effect transistor according to the present invention may be materialized with a device structure in which either one of the second and third semiconductor layers is omitted.